The present invention relates to telecommunications in general, and, more particularly, to an apparatus for converting one or more parallel words into one or more serialized streams of bits and back again into parallel words.
There are situations where parallel words of data need to be transmitted via a serial communications channel. In these situations, a first apparatus converts the words into a serialized stream of bits for transmission on the serial communications channel. Typically the first apparatus is known as a serializer.
At the receiving end of the serial communications channel, a second apparatus captures the serialized stream of bits and restores it back into parallel words. Typically, the second apparatus is known as a deserializer. Regardless of what the first apparatus and the second apparatus are called, the second apparatus performs the inverse operation of the first apparatus.
FIG. 1 depicts a block diagram of serial communications system 100 in the prior art, which comprises: serializer 101, deserializer 102, timing source 103, timing source 104, and serial communications channel 111, interconnected as shown.
Serializer 101 receives a parallel word of bits and a timing signal (e.g., a clock signal, etc.) from timing source 103 and converts the parallel word into a serialized stream of bits for transmission via serial communications channel 111. For example, serializer 101 can comprise a parallel-load-in/serial-shift-out register that loads words in at a slower rate than it shifts bits out.
Serial communications channel 111 is a logical channel that can be carried alone on a physical channel or can be multiplexed with other logical channels on a physical channel (e.g., a metal wireline, an optical fiber, or a wireless channel, etc.).
Deserializer 102 receives the serialized stream of bits from serial communications channel 111 and a clock signal from timing source 104, captures the serialized stream of bits, and converts it back into a parallel word. For example, deserializer 102 can comprise a serial-shift-in/parallel-unload-out shift register.
The design and operation of serializer 101 and deserializer 102 can be problematic. For example, if a bit error occurs during the transmission of the serialized stream of bits, the error might not be detected or corrected by the deserializer. Furthermore, if the word is broken up and its pieces are sent via different serial communications channels, the deserializer can fail to properly reassemble the fragments back into a word.
Therefore, the need exists for a serializer and a deserializer that are capable of detecting and/or correcting one or more bit errors that occur during the transmission of the serialized stream of bits. Furthermore, the need exists for a serializer and a deserializer that are capable of breaking up a word into pieces for transmission via different serial communications channels and of properly reassembling the fragments back into a word.
Some embodiments of the present invention enable the serialization of words without some of the costs and disadvantages for doing so in the prior art. For example, the illustrative embodiment provides an efficient scheme for forward error correction (i.e., the correction of bit errors by the receiver without the retransmission of the data by the transmitter). In particular, the illustrative embodiment provides an efficient method for generating row and column parity bits for an S by K-bit matrix that can, in some cases, require fewer than S+K parity bits.
Furthermore, the illustrative embodiment provides both symbol alignment and frame alignment by the deserializer in an efficient manner. This is particularly useful for when a single word is broken up and its pieces are sent via different serial communications channels and the deserializer needs to be capable of properly reassembling the fragments into the word.
The illustrative embodiment comprises: receiving a matrix C of bits, wherein the matrix C has dimensions of S by K and wherein both S and K are positive integers; generating a plurality of row parity bits that are indicative of the parity of a row of bits in a matrix D that has dimensions of S/y by yK, wherein S/y and yK are positive integers, wherein y is a positive integer other than one, and wherein matrix D is based on a shuffling function of matrix C; and transmitting the matrix C of bits and the plurality of row parity bits.